This 32-lane switch is configured with six ports – one upstream x8 Gen 2 port and five downstream ports. It shows a Gen 2-enabled server chipset with two PCIe ports on the root complex, one of which (the x8 port) is connected to a Gen 2 switch. Here, the switch can act as bridge, as shown in Fig. PCIe Gen 2 offers twice the maximum throughput with the same number of lanes and there is now a need for something to bridge between the two standards. A Gen 2 switch acts like a “bridge” from Gen 1 I/Os to a Gen 2 root complex. Some bridges are also available with a “reverse mode” configuration option, which allows the creation of PCIe slots from existing PCI slots useful for updating legacy motherboards.įig.
This is done using the commonly available “forward mode” bridge configuration. PCIe-to-PCI bridges enable the creation of additional PCI or PCI-X slots on system boards and riser cards. For most applications, the transition to PCIe from PCI has brought the benefits of cost and power reductions, smaller form factor due to lowered pin count, and increased performance.Īs a result, system boards and chipsets now have several PCIe slots but limited PCI connectivity. The conventional PCI bus delivered a low-cost, robust and well understood interconnect standard. The outlook for the PCIe-to-PCI bridge function And, further complicating matters, some companies have decided to call their PCIe switches “bridges.” Once the majority of these endpoints go PCIe-native, as expected, the interconnect role once largely held by bridges will shift to switches, though bridges will continue to enable legacy PCI designs in the PCIe world.Īdding another dimension to this shift, designs are now migrating to PCIe Gen 2, and its 5 GT/s performance, for next-generation interconnect. Switches expand into bridging, and Gen 2 offers simplification opportunitiesĪs the I/O interconnect world has transitioned from PCI to PCI Express (PCIe), bridge ICs have filled a critical role: to allow designers to continue to use existing PCI and PCI-X endpoints in PCIe-based systems.